General Register Organization and ALU Control Word

What is General Register Organization? (In Simple Words)

In early, basic computers, the CPU had only one main working register: the Accumulator (AC).

Every single math problem had to pass through this single register.
This created a huge traffic jam (bottleneck) inside the CPU!

Modern CPUs solve this by having a group of multiple general-purpose registers (R₁ to R₇).

We call this General Register Organization (GRO).
Any register can supply inputs to the ALU, and any register can receive the calculated answer!

💡 Real-Life Indian Student Analogy:
Think of a college library.
If there is only 1 book-issue counter, all students must stand in one long line (like an Accumulator CPU).
If the library opens 7 separate service counters (R₁ to R₇), students get served instantly without waiting!

1. Block Diagram of General Register Organization

The system has 4 main hardware components:

7 General Purpose Registers: R₁ through R₇ to store intermediate data.
Two Multiplexer Buses (Bus A and Bus B): Select two registers to send data into the ALU.
Arithmetic Logic Unit (ALU): Performs the requested math or logic operation.
Destination Decoder (3-to-8 Line): Chooses which register will save the ALU result.

Data Path in General Register Organization

Registers (R₁-R₇) → MUX A & MUX B

→ Arithmetic Logic Unit (ALU)

→ Destination Decoder → Stored in Destination Register

2. The 14-Bit Control Word

To command this entire register bank during one single clock tick, the CPU issues a 14-bit binary command called a Control Word:

14-Bit Control Word Structure

SELA (3 Bits)

Selects source register for Bus A

SELB (3 Bits)

Selects source register for Bus B

SELD (3 Bits)

Selects destination register to save result

OPR (5 Bits)

Selects ALU operation (ADD, SUB, AND, OR)

Register Selection Encoding:

3-Bit Code	SELA (Bus A)	SELB (Bus B)	SELD (Destination)
`000`	External Input (IN)	External Input (IN)	None (Do not store)
`001`	R₁	R₁	R₁
`010`	R₂	R₂	R₂
`011`	R₃	R₃	R₃
`100`	R₄	R₄	R₄
`101`	R₅	R₅	R₅
`110`	R₆	R₆	R₆
`111`	R₇	R₇	R₇

ALU Operation Codes (Sample OPR):

00010: ADD (A + B)
00101: SUB (A - B)
00110: INCA (A + 1)
01010: AND (A AND B)
01100: OR (A OR B)
01110: XOR (A XOR B)

3. Solved Control Word Problem

Problem: Find the 14-bit control word to perform:
R₁ ← R₂ + R₃

Step-by-Step Field Resolution:

Bus A Source: Register R₂ → Code is 010
Bus B Source: Register R₃ → Code is 011
Destination: Register R₁ → Code is 001
Operation: ADD → Code is 00010

Final Control Word:

SELA (3 bits)	SELB (3 bits)	SELD (3 bits)	OPR (5 bits)
010	011	001	00010

Complete 14-bit Binary Word: 010 011 001 00010
In Hexadecimal notation: 2 6 2 2

💡 DAVV Exam Preparation Tips

5-Mark Question: “What is a control word in General Register Organization? Explain the significance of SELA, SELB, SELD, and OPR fields.”

Draw the 14-bit field allocation diagram.

Explain the 4 fields in simple terms:

SELA (3 bits): Selects input for Bus A

SELB (3 bits): Selects input for Bus B

SELD (3 bits): Selects destination register

OPR (5 bits): Tells ALU which math or logic operation to run

10-Mark Question: “Explain General Register Organization with a neat block diagram showing 7 registers, MUX A, MUX B, ALU, and Decoder. Formulate the control words for: (i) R₁ ← R₂ + R₃ and (ii) R₄ ← R₅ - R₆.”

Draw the complete data path diagram with 7 registers, 2 MUXes, ALU, and 3-to-8 decoder.

Show the binary breakdown for both operations:

R₁ ← R₂ + R₃: SELA=010, SELB=011, SELD=001, OPR=00010.

R₄ ← R₅ - R₆: SELA=101, SELB=110, SELD=100, OPR=00101.

Combine the bits into final binary and hex strings.

General Register Organization & ALU Control Word