Instruction Cycle, Timing and Control, and Memory-Reference Instructions

What is the Instruction Cycle? (In Simple Words)

Whenever you click Run on a C, C++, or Java program, the CPU processes your code line by line.

• The CPU runs a continuous loop called the Instruction Cycle.
• Every single instruction goes through 4 essential phases:
  1. Fetch: Bring the instruction from RAM memory into the CPU.
  2. Decode: Find out what the instruction wants to do.
  3. Read Effective Address: If indirect addressing is used, fetch the real operand pointer.
  4. Execute: Perform the actual calculation or action.

💡 Real-Life Indian Student Analogy:
Think of ordering food at a restaurant:

1. The waiter takes your written order slip (Fetch).
2. The chef reads what dish you ordered (Decode).
3. The helper fetches the spices and vegetables from the pantry (Read Address/Data).
4. The chef cooks and serves the dish (Execute)!

1. Timing and Control Unit

Inside the CPU, timing is controlled by a master clock and a Sequence Counter (SC):

• The Sequence Counter counts from 0 to 15.
• A 4-to-16 Line Decoder splits this count into 16 separate timing signals: T₀, T₁, T₂, …, T₁₅.
• Each timing step stays active for exactly one clock tick.
• Once an instruction finishes executing, the control unit resets the counter (SC ← 0) to begin the next instruction at T₀.

2. Step-by-Step Instruction Cycle Micro-operations

Detailed Micro-operations:

• At T₀: AR ← PC
  (Send the address from Program Counter to Address Register).
• At T₁: IR ← M[AR], PC ← PC + 1
  (Read the instruction from memory into Instruction Register, and step the PC to the next line).
• At T₂: Decode Opcode bits 12-14 into D₀ through D₇, copy address bits 0-11 to AR, and load mode bit 15 into flip-flop I.
• At T₃: If I = 1 (Indirect addressing), read the real pointer: AR ← M[AR]. If I = 0, the address is already direct.

3. Seven Memory-Reference Instructions

When the opcode decoder produces D₀ to D₆, the instruction accesses RAM memory:

1. AND (D₀): Logical AND with Accumulator

• RTL:
  D₀T₄: DR ← M[AR]
D₀T₅: AC ← AC AND DR, SC ← 0
• Performs bitwise AND between Accumulator (AC) and data from memory.

2. ADD (D₁): Binary Addition

• RTL:
  D₁T₄: DR ← M[AR]
D₁T₅: AC ← AC + DR, E ← Cout, SC ← 0
• Adds memory data to AC, storing the carry-out bit in flip-flop E.

3. LDA (D₂): Load Accumulator

• RTL:
  D₂T₄: DR ← M[AR]
D₂T₅: AC ← DR, SC ← 0
• Copies data from memory into AC.

4. STA (D₃): Store Accumulator

• RTL:
  D₃T₄: M[AR] ← AC, SC ← 0
• Writes the value of AC into RAM memory at location AR.

5. BUN (D₄): Branch Unconditionally (Go To)

• RTL:
  D₄T₄: PC ← AR, SC ← 0
• Jumps program execution straight to address AR (like goto in C).

6. BSA (D₅): Branch and Save Return Address (Function Call)

• When calling a function, the computer must remember where to return:
• RTL:
  D₅T₄: M[AR] ← PC, AR ← AR + 1
D₅T₅: PC ← AR, SC ← 0
• Saves the return address into memory, and jumps execution to the function body at AR + 1.

7. ISZ (D₆): Increment and Skip if Zero (Loop Control)

• RTL:
  D₆T₄: DR ← M[AR]
D₆T₅: DR ← DR + 1
D₆T₆: M[AR] ← DR, if (DR = 0) then (PC ← PC + 1), SC ← 0
• Adds 1 to a memory counter. If the counter reaches zero, it skips the next jump instruction to exit the loop!

💡 DAVV Exam Preparation Tips

5-Mark Question: “Explain the Fetch and Decode phases of an instruction cycle with Register Transfer Language (RTL) equations.”

• Write down the exact RTL equations:
  T₀: AR ← PC
T₁: IR ← M[AR], PC ← PC + 1
T₂: D₀...D₇ ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15).
• Clearly explain what each register holds during these three clock ticks.

10-Mark Question: “Explain all memory-reference instructions in a basic computer with their register transfer micro-operations and timing signals.”

• List all 7 instructions: AND, ADD, LDA, STA, BUN, BSA, and ISZ.
• Write the timing steps (T₄, T₅, T₆) for each instruction.
• Give extra explanation to BSA: how it saves the return address into M[AR] and branches to AR + 1.