Data Transfer Schemes: Programmed I/O, Interrupts, DMA, and IOP

Introduction: Moving Data Between Peripherals and Memory

Transferring files between external drives (SSDs, USB pen drives) and RAM memory needs to be fast and efficient.

Over the years, four data transfer methods were invented to balance CPU speed and hardware costs:

1. Programmed I/O (Polling)

• The CPU executes an instruction that checks if the device is ready.
• If the device is busy, the CPU gets trapped in an infinite waiting loop (Busy-Waiting):

  CHECK: SKI             ; Has the user pressed a key?
         BUN CHECK       ; No? Loop right back and keep checking!
         INP             ; Yes! Read the key into Accumulator

• Huge Drawback: Wastes almost all CPU processing power waiting for slow humans or mechanical disks.

2. Interrupt-Initiated I/O

• The CPU does not ask the device anything. It continues executing normal user programs.
• When the device is ready with data, it sends an electrical Interrupt Request (INTR) to the CPU.
• The CPU pauses its current program, saves its PC return address on the stack, and runs the Interrupt Service Routine (ISR) to copy the data.
• Once finished, the CPU returns right back to its original program.

Daisy Chaining (Priority Resolution):

When multiple devices ask for attention at the same time, a Daisy Chain connects them like a series line of students.

• The device physically closest to the CPU has the highest priority and gets served first!

3. Direct Memory Access (DMA Transfer)

When loading a large 4 GB movie or game file from an SSD into RAM, having the CPU move each byte one-by-one through its Accumulator is painfully slow.

Direct Memory Access (DMA) lets an external chip (the DMA Controller) transfer blocks of data directly between the drive and RAM without involving the CPU at all!

Key Registers Inside a DMA Controller:

1. Address Register: Stores the starting RAM memory address where data must go.
2. Word Count Register: Stores how many bytes to transfer (counts down to zero).
3. Control Register: Sets the direction (Read from disk or Write to disk).

Two Main DMA Modes:

• Burst Transfer (Block Mode):
  The DMA controller grabs the whole bus and transfers thousands of bytes without stopping. The CPU pauses until the transfer finishes.
• Cycle Stealing:
  The DMA controller “steals” just one single memory clock tick while the CPU is busy doing internal ALU math. The CPU barely notices any slowdown, and data streams continuously into RAM!

4. Input-Output Processor (IOP)

In enterprise mainframes and web servers, an I/O Processor (IOP) is a dedicated separate mini-CPU.

• The main CPU simply tells the IOP: “Load this 10 GB database from disk into RAM.”
• The IOP handles everything independently: addresses, error checks, buffers, and bus management.
• When the transfer is 100% complete, it sends one final interrupt to let the main CPU know!

💡 DAVV Exam Preparation Tips

5-Mark Question: “What is DMA? Differentiate between Cycle Stealing mode and Burst Transfer mode.”

• Define DMA: Direct high-speed data transfer between RAM and devices bypassing the CPU.
• Contrast the 2 modes:
  • Burst Mode: Transfers the whole file block at once while CPU is held paused.
  • Cycle Stealing: Steals 1 memory cycle at a time between CPU instruction steps without pausing the CPU.

10-Mark Question: “Explain the four primary data transfer schemes: Programmed I/O, Interrupt-Initiated I/O, DMA, and IOP. Draw the block diagram of a DMA controller.”

• Clearly explain all 4 methods with their pros and cons.
• Draw the DMA Controller diagram showing:
  • Address Register
  • Word Count Register
  • Control Register
  • Bus Request (BR) and Bus Grant (BG) control handshake pins.
• Summarize all 4 schemes in a quick comparison table.