Virtual Memory, Paging, Address Translation, and Memory Interleaving

What is Virtual Memory? (In Simple Words)

In early computers, if a heavy software or game required 16 GB of RAM but your computer only had 8 GB of RAM, the system would crash with an Out of Memory error!

Virtual Memory solves this problem completely:

• It is a smart partnership between CPU hardware (the MMU - Memory Management Unit) and the Operating System (Windows/Linux).
• It creates the magic illusion that your computer has a massive, limitless pool of RAM.
• It does this by secretly using a section of your fast SSD or hard disk as an emergency overflow reservoir!

💡 Real-Life Indian Student Analogy:
Think of your college study desk:
Your small desk only has room for 4 notebooks at a time (like physical RAM).
But you have 20 notebooks in your college bag under the desk (like the SSD).
Whenever you need a new notebook, you swap it with one from your bag! Your desk feels infinitely large.

1. Logical Address vs. Physical Address

• Logical (Virtual) Address: The memory address generated by the CPU while executing your program code. The entire collection of logical addresses is called the Virtual Address Space.
• Physical Address: The actual hardware pin address in the physical DRAM chips. The total range of real RAM addresses is called the Physical Memory Space.

2. Paging and Address Translation

In a Paging system:

1. Virtual memory is chopped into equal-sized blocks called Pages (typically 4 KB each).
2. Physical RAM is chopped into slots of the exact same size called Page Frames.

How Address Translation Works:

• The CPU gives a virtual address containing two parts: Page Number (p) and Offset (d).
• The Offset (d) specifies the exact byte inside the page and passes straight through untouched.
• The Page Number (p) looks up an entry in the Page Table.
• The Page Table returns the physical Frame Number (f).
• Combine f and d to get the final real address in physical DRAM!

3. What is a Page Fault?

When the CPU requests a virtual page that is currently sitting on the SSD and has not yet been copied into physical RAM, a Page Fault occurs!

5-Step Page Fault Handling:

1. Trap: The CPU hardware triggers an internal alarm called a Page Fault.
2. Pause: The CPU halts the user program and calls the Operating System kernel.
3. Locate on Disk: The OS finds the missing page on the secondary SSD.
4. Frame Replacement: If physical RAM is full, the OS evicts an unused page using a replacement rule like LRU (Least Recently Used).
5. Load & Resume: The missing page is copied into the empty RAM frame, the Page Table is updated, and the CPU restarts the trapped instruction!

4. Memory Interleaving

Reading or writing to a DRAM memory chip requires a tiny recharge time. If the CPU accesses consecutive words from the same DRAM module, it must wait!

Memory Interleaving divides main RAM into multiple independent banks (e.g. Bank 0, Bank 1, Bank 2, Bank 3):

• Low-Order Interleaving: Consecutive addresses are spread across different banks:
  • Address 0 is in Bank 0
  • Address 1 is in Bank 1
  • Address 2 is in Bank 2
  • Address 3 is in Bank 3
• Result: The CPU can read from all 4 banks at the exact same time, multiplying memory transfer speeds by up to 400%!

💡 DAVV Exam Preparation Tips

5-Mark Question: “What is a Page Fault? Describe the sequence of steps that occur when a page fault happens.”

• Define page fault: CPU requests a page whose valid bit in the page table is 0 (not in RAM).
• List the 5-step OS handling procedure:
  1. Hardware trap to OS
  2. Save program state
  3. Find page on SSD
  4. Evict old page using LRU and load new page into RAM
  5. Update page table and resume execution.

10-Mark Question: “Explain Virtual Memory with paging. Draw the address translation hardware architecture showing page number, frame number, and offset. What is Memory Interleaving?”

• Draw the translation diagram mapping Logical Address (p, d) to Physical Address (f, d) using the Page Table.
• Define Page, Frame, and Page Table.
• Explain Low-Order Memory Interleaving with a neat 4-bank diagram showing how consecutive addresses are interleaved across banks.