Registers, Shift Registers, and Bidirectional Shift Registers with Parallel Load

What is a Register? (In Simple Words)

A single flip-flop can store only 1 bit (0 or 1).

But computers process data in groups: bytes (8 bits) or words (16, 32, or 64 bits).
A Register is simply a group of flip-flops working together to store multi-bit binary numbers.
For example, a 4-bit register has 4 flip-flops and can store any number from 0 to 15.

💡 Real-Life Indian Student Analogy:
Think of a classroom bench.
One individual chair holds only 1 student (like a single flip-flop).
A 4-seater bench holds 4 students seated side-by-side (like a 4-bit register)!

1. 4-Bit Register with Parallel Load

In a normal register, every clock tick might overwrite the stored data.

But the CPU doesn’t want to change data on every tick!
It only wants to load new data when a command signal called LOAD is turned ON (LOAD = 1).

4-Bit Parallel Load Register Architecture

When LOAD = 0

A 2-to-1 MUX feeds output Q right back into input D. The register holds its current value safely (No change).

When LOAD = 1

The 2-to-1 MUX passes new data from outside into input D. All 4 bits load in parallel at the same clock tick!

How It Is Built:

Uses four D flip-flops (FF₀ to FF₃).
Each flip-flop has a 2-to-1 Multiplexer in front of its input.
When LOAD = 0: The old stored bit loops back to input D. The value stays untouched.
When LOAD = 1: The external input bits (I₀, I₁, I₂, I₃) pass through to D. All 4 bits load together in one single clock cycle!
A common Clear line resets all flip-flops to 0000 whenever needed.

2. Four Modes of Shift Registers

A Shift Register can slide its stored bits one step to the left or right with every clock pulse.

The Four Shift Register Configurations

1. SISO

Serial-In Serial-Out
Data enters bit-by-bit and leaves bit-by-bit. Slowest; used for delays.

2. SIPO

Serial-In Parallel-Out
Data enters bit-by-bit and reads out all at once. Used in serial converters.

3. PISO

Parallel-In Serial-Out
Data loads all at once and transmits one bit at a time. Used in USB/COM ports.

4. PIPO

Parallel-In Parallel-Out
Loads all at once and outputs all at once. Fastest; used inside CPU registers!

3. Bidirectional Shift Register with Parallel Load

A Bidirectional Shift Register (also called a Universal Shift Register) can do all operations in one chip:

Shift Right: Slides bits to the right (This divides a binary number by 2!).
Shift Left: Slides bits to the left (This multiplies a binary number by 2!).
Parallel Load: Loads all bits at once.
Hold (No Change): Keeps current data untouched.

It uses four D flip-flops, each connected to a 4-to-1 Multiplexer. Two mode select lines (S₁, S₀) control the operation:

Control Function Table:

Select S₁	Select S₀	Mode	What It Does
0	0	No Change	Output loops back to input. Data stays stored.
0	1	Shift Right	Bits move right (`A₃ → A₂ → A₁ → A₀`). Serial input enters at the left.
1	0	Shift Left	Bits move left (`A₀ → A₁ → A₂ → A₃`). Serial input enters at the right.
1	1	Parallel Load	All 4 external input bits (`I₀, I₁, I₂, I₃`) load at once.

💡 DAVV Exam Preparation Tips

5-Mark Question: “What is a 4-bit register with parallel load? Draw its logic circuit diagram and explain its operation.”

Draw 4 D flip-flops with 2-to-1 multiplexers in front of each input.

Clearly show what happens:

LOAD = 0: Output Q loops back into D (Hold state).

LOAD = 1: External inputs I enter D (Parallel load).

Mention the shared Clock and Clear lines.

10-Mark Question: “Explain the design and operation of a 4-bit Bidirectional Shift Register with Parallel Load (Universal Shift Register). Provide the function table and circuit diagram.”

Write down the 4-case Function Table for S₁ S₀ (00, 01, 10, 11).

Explain the 4 connections for each 4-to-1 MUX:

Input 0 = Hold (from its own Q)

Input 1 = Shift Right (from left neighbor)

Input 2 = Shift Left (from right neighbor)

Input 3 = Parallel input I

Point out the math trick: Shifting left multiplies by 2, and shifting right divides by 2!

Registers, Shift Registers & Bidirectional Shift Register